This invention relates to phase lock loops and, in particular, to dual-loop phase lock loops.
Clock recovery circuits are required in many of today""s high speed integrated circuit devices to generate a clock signal having a certain timing relationship with a reference signal. Clock recovery circuits can be employed to generate clock signals having a synchronous, controlled and/or predetermined relationship with a reference signal such as an external clock signal. By integrating clock recovery circuitry into a clock system of, for example, a microprocessor or synchronous memory device, difficulties relating to maintaining or ensuring signal integrity and clock skew can be overcome. In addition, reliable clocking operations which support very high speed circuit implementations can be achieved.
One type of a clock recovery circuit is a phase lock loop (PLL). A phase lock loop circuit, for example, utilizes a voltage controlled oscillator (VCO) to generate a recovered clock signal having a certain timing relationship with a reference signal. A dual loop phase lock loop can incorporate so-called phase mixers (more appropriately termed xe2x80x9cphase adjustersxe2x80x9d) in a second loop of the PLL. The phase mixers are associated with voltage controlled oscillator and can provide a feedback loop to a suitable phase frequency detector which detects differences in the phase frequency between the output of the phase mixers (an internal clock) and a reference clock (an external clock).
One problem associated with dual loop phase lock loops is that of trying to maintain high loop bandwidth for the inner analog PLL loop while maintaining low power consumption. Accordingly, this invention arose out of concerns associated with providing improved dual loop phase lock loops having a suitably high inner loop bandwidth while maintaining low power consumption.